//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++

THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name: 

        SC4240PDD.H

Abstract:

       Samsung S3SC2440 USB Function Platform-Dependent Driver header.

--*/

#ifndef _SC2440PDD_H_
#define _SC2440PDD_H_

#include <windows.h>
#include <ceddk.h>
#include <usbfntypes.h>
#include <usbfn.h>



#ifndef SHIP_BUILD
#define STR_MODULE _T("SC2440UsbFn!")
#define SETFNAME() LPCTSTR pszFname = STR_MODULE _T(__FUNCTION__) _T(":")
#else
#define SETFNAME()
#endif

#define SET_ADDRESS_REG_OFFSET      0x0
#define PWR_REG_OFFSET              0x4
#define EP_INT_REG_OFFSET           0x8
#define USB_INT_REG_OFFSET          0x18
#define EP_INT_EN_REG_OFFSET        0x1C
#define USB_INT_EN_REG_OFFSET       0x2C

#define EP0_FIFO_REG_OFFSET        0x80
#define EP1_FIFO_REG_OFFSET        0x84
#define EP2_FIFO_REG_OFFSET        0x88
#define EP3_FIFO_REG_OFFSET        0x8C
#define EP4_FIFO_REG_OFFSET        0x90
 
#define IDXADDR_REG_OFFSET          0x38
// Indexed Registers
#define MAX_PKT_SIZE_REG_OFFSET     0x40
#define EP0_CSR_REG_OFFSET          0x44
#define IN_CSR1_REG_OFFSET          0x44
#define IN_CSR2_REG_OFFSET          0x48
#define OUT_CSR1_REG_OFFSET         0x50
#define OUT_CSR2_REG_OFFSET         0x54
#define OUT_FIFO_CNT1_REG_OFFSET    0x58
#define OUT_FIFO_CNT2_REG_OFFSET    0x5C

// DMA interface control register
#define EP1_DMA_CON_OFFSET			0xC0
#define EP2_DMA_CON_OFFSET			0xD8
#define EP3_DMA_CON_OFFSET			0x100
#define EP4_DMA_CON_OFFSET			0x118

// DMA unit counter register
#define EP1_DMA_UNIT_OFFSET			0xC4
#define EP2_DMA_UNIT_OFFSET			0xDC
#define EP3_DMA_UNIT_OFFSET			0x104
#define EP4_DMA_UNIT_OFFSET			0x11C

// DMA fifo counter register
#define EP1_DMA_FIFO_OFFSET			0xC8
#define EP2_DMA_FIFO_OFFSET			0xE0
#define EP3_DMA_FIFO_OFFSET			0x108
#define EP4_DMA_FIFO_OFFSET			0x120

// DMA total transfer counter register
#define EP1_DMA_TTC_L_OFFSET		0xCC
#define EP1_DMA_TTC_M_OFFSET		0xD0
#define EP1_DMA_TTC_H_OFFSET		0xD4
#define EP2_DMA_TTC_L_OFFSET		0xE4
#define EP2_DMA_TTC_M_OFFSET		0xE8
#define EP2_DMA_TTC_H_OFFSET		0xEC
#define EP3_DMA_TTC_L_OFFSET		0x10C
#define EP3_DMA_TTC_M_OFFSET		0x110
#define EP3_DMA_TTC_H_OFFSET		0x114
#define EP4_DMA_TTC_L_OFFSET		0x124
#define EP4_DMA_TTC_M_OFFSET		0x128
#define EP4_DMA_TTC_H_OFFSET		0x12C

//
#define BASE_REGISTER_OFFSET        0x140
#define REGISTER_SET_SIZE           0x200

// Power Reg Bits
#define USB_RESET                   0x8
#define SUSPEND_MODE_ENABLE_CTRL    0x1

// EP0 CSR
#define EP0_OUT_PACKET_RDY          0x1
#define EP0_IN_PACKET_RDY           0x2
#define DATA_END                    0x8
#define SETUP_END                   0x10
#define SERVICED_OUT_PKY_RDY        0x40
#define SERVICED_SETUP_END          0x80

// IN_CSR1_REG Bit definitions
#define IN_PACKET_READY             0x1
#define UNDER_RUN                   0x4   // Iso Mode Only
#define FLUSH_IN_FIFO               0x8
#define IN_SEND_STALL               0x10
#define IN_SENT_STALL               0x20
#define IN_CLR_DATA_TOGGLE          0x40

// OUT_CSR1_REG Bit definitions
#define OUT_PACKET_READY            0x1
#define FLUSH_OUT_FIFO              0x10
#define OUT_SEND_STALL              0x20
#define OUT_SENT_STALL              0x40
#define OUT_CLR_DATA_TOGGLE         0x80

// IN_CSR2_REG Bit definitions
#define IN_DMA_INT_DISABLE          0x10
#define SET_MODE_IN                 0x20 
#define SET_TYPE_ISO                0x40  // Note that Samsung does not currently support ISOCH 
#define AUTO_MODE                   0x80

// OUT_CSR2_REG Bit definitions
#define AUTO_CLR					0x40
#define OUT_DMA_INT_DISABLE         0x20

// Can be used for Interrupt and Interrupt Enable Reg - common bit def
#define EP0_INT_INTR                0x1
#define EP1_INT_INTR                0x2
#define EP2_INT_INTR                0x4
#define EP3_INT_INTR                0x8
#define EP4_INT_INTR                0x10

#define CLEAR_ALL_EP_INTRS          (EP0_INT_INTR | EP1_INT_INTR | EP2_INT_INTR | EP3_INT_INTR | EP4_INT_INTR)

#define  EP_INTERRUPT_DISABLE_ALL   0x0   // Bits to write to EP_INT_EN_REG - Use CLEAR

// Bit Definitions for USB_INT_REG and USB_INT_EN_REG_OFFSET
#define USB_RESET_INTR              0x4
#define USB_RESUME_INTR             0x2
#define USB_SUSPEND_INTR            0x1

// DMA control register bit definitions
#define RUN_OB						0x80
#define STATE						0x70
#define DEMAND_MODE					0x8
#define OUT_DMA_RUN					0x4
#define IN_DMA_RUN					0x2
#define DMA_MODE_EN					0x1

//
#define REAL_PHYSICAL_ADDR_EP0_FIFO		(0x520001c0) //Endpoint 0 FIFO
#define REAL_PHYSICAL_ADDR_EP1_FIFO		(0x520001c4) //Endpoint 1 FIFO
#define REAL_PHYSICAL_ADDR_EP2_FIFO		(0x520001c8) //Endpoint 2 FIFO
#define REAL_PHYSICAL_ADDR_EP3_FIFO		(0x520001cc) //Endpoint 3 FIFO
#define REAL_PHYSICAL_ADDR_EP4_FIFO		(0x520001d0) //Endpoint 4 FIFO

#define DMA_BUFFER_BASE					0xAC000000
#define DMA_PHYSICAL_BASE				0x30000000
#define DRIVER_GLOBALS_PHYSICAL_MEMORY_START  (DMA_BUFFER_BASE + 0x10000)

// We poll for device detach at the following rate.
#define S3C2440_USB_POLL_RATE 1000

// For USB DMA
BOOL InitUsbdDriverGlobals(void);  	//:-)
void UsbdDeallocateVm(void);	   	//:-)
BOOL UsbdAllocateVm(void);	   		//:-)
void UsbdInitDma(int epnum, int bufIndex,int bufOffset);	//:-)

//Visual.Wei: register address
#define USB_FUNC_BASS 0x52000000
#define USB_REG(offset) (*(volatile unsigned char *)(USB_FUNC_BASS+offset))	

#define rFUNC_ADDR_REG		USB_REG(0x0140)	//Function address
#define rPWR_REG			USB_REG(0x0144)	//Power management
#define rEP_INT_REG			USB_REG(0x0148)	//EP Interrupt pending and clear
#define rUSB_INT_REG		USB_REG(0x0158)	//USB Interrupt pending and clear
#define rEP_INT_EN_REG		USB_REG(0x015c)	//Interrupt enable
#define rUSB_INT_EN_REG	USB_REG(0x016c)
#define rFRAME_NUM1_REG	USB_REG(0x0170)	//Frame number lower byte
#define rFRAME_NUM2_REG	USB_REG(0x0174)	//Frame number higher byte
#define rINDEX_REG			USB_REG(0x0178)	//Register index
#define rMAXP_REG			USB_REG(0x0180)	//Endpoint max packet
#define rEP0_CSR				USB_REG(0x0184)	//Endpoint 0 status
#define rIN_CSR1_REG		USB_REG(0x0184)	//In endpoint control status
#define rIN_CSR2_REG		USB_REG(0x0188)
#define rOUT_CSR1_REG		USB_REG(0x0190)	//Out endpoint control status
#define rOUT_CSR2_REG		USB_REG(0x0194)
#define rOUT_FIFO_CNT1_REG	USB_REG(0x0198)	//Endpoint out write count
#define rOUT_FIFO_CNT2_REG	USB_REG(0x019c)
#define rEP0_FIFO			USB_REG(0x01c0)	//Endpoint 0 FIFO
#define rEP1_FIFO			USB_REG(0x01c4)	//Endpoint 1 FIFO
#define rEP2_FIFO			USB_REG(0x01c8)	//Endpoint 2 FIFO
#define rEP3_FIFO			USB_REG(0x01cc)	//Endpoint 3 FIFO
#define rEP4_FIFO			USB_REG(0x01d0)	//Endpoint 4 FIFO
#define rEP1_DMA_CON		USB_REG(0x0200)	//EP1 DMA interface control
#define rEP1_DMA_UNIT		USB_REG(0x0204)	//EP1 DMA Tx unit counter
#define rEP1_DMA_FIFO		USB_REG(0x0208)	//EP1 DMA Tx FIFO counter
#define rEP1_DMA_TTC_L		USB_REG(0x020c)	//EP1 DMA total Tx counter
#define rEP1_DMA_TTC_M		USB_REG(0x0210)
#define rEP1_DMA_TTC_H		USB_REG(0x0214)
#define rEP2_DMA_CON		USB_REG(0x0218)	//EP2 DMA interface control
#define rEP2_DMA_UNIT		USB_REG(0x021c)	//EP2 DMA Tx unit counter
#define rEP2_DMA_FIFO		USB_REG(0x0220)	//EP2 DMA Tx FIFO counter
#define rEP2_DMA_TTC_L		USB_REG(0x0224)	//EP2 DMA total Tx counter
#define rEP2_DMA_TTC_M		USB_REG(0x0228)
#define rEP2_DMA_TTC_H		USB_REG(0x022c)
#define rEP3_DMA_CON		USB_REG(0x0240)	//EP3 DMA interface control
#define rEP3_DMA_UNIT		USB_REG(0x0244)	//EP3 DMA Tx unit counter
#define rEP3_DMA_FIFO		USB_REG(0x0248)	//EP3 DMA Tx FIFO counter
#define rEP3_DMA_TTC_L		USB_REG(0x024c)	//EP3 DMA total Tx counter
#define rEP3_DMA_TTC_M		USB_REG(0x0250)
#define rEP3_DMA_TTC_H		USB_REG(0x0254)
#define rEP4_DMA_CON		USB_REG(0x0258)	//EP4 DMA interface control
#define rEP4_DMA_UNIT		USB_REG(0x025c)	//EP4 DMA Tx unit counter
#define rEP4_DMA_FIFO		USB_REG(0x0260)	//EP4 DMA Tx FIFO counter
#define rEP4_DMA_TTC_L		USB_REG(0x0264)	//EP4 DMA total Tx counter
#define rEP4_DMA_TTC_M		USB_REG(0x0268)
#define rEP4_DMA_TTC_H		USB_REG(0x026c)


//*************************************************************************
// USB definitons
//*************************************************************************

/* Power Management Register */
#define DISABLE_SUSPEND          0x00   
#define ENABLE_SUSPEND           0x01
#define SUSPEND_MODE		 0x02
#define MCU_RESUME               0x04
#define ISO_UPDATE		 (1<<7)

/* MAXP Register */
#define FIFO_SIZE_0              0x00  /* 0x00 * 8 = 0  */
#define FIFO_SIZE_8              0x01  /* 0x01 * 8 = 8  */
#define FIFO_SIZE_16             0x02  /* 0x02 * 8 = 16 */
#define FIFO_SIZE_32             0x04  /* 0x04 * 8 = 32 */
#define FIFO_SIZE_64             0x08  /* 0x08 * 8 = 64 */

/* ENDPOINT0 CSR (Control Status Register) : Mapped to IN CSR1 */
#define EP0_OUT_PKT_READY        0x01  /* USB sets, MCU clears by setting SERVICED_OUT_PKT_RDY */
#define EP0_IN_PKT_READY         0x02  /* MCU sets, USB clears after sending FIFO */
#define EP0_SENT_STALL           0x04  /* USB sets */       
#define EP0_DATA_END             0x08  /* MCU sets */
#define EP0_SETUP_END            0x10  /* USB sets, MCU clears by setting SERVICED_SETUP_END */
#define EP0_SEND_STALL           0x20  /* MCU sets */
#define EP0_SERVICED_OUT_PKT_RDY 0x40  /* MCU writes 1 to clear OUT_PKT_READY */
#define EP0_SERVICED_SETUP_END   0x80  /* MCU writes 1 to clear SETUP_END        */

#define EP0_WR_BITS              0xc0  

//EP_INT_REG / EP_INT_EN_REG
#define EP0_INT                	 0x01  // Endpoint 0, Control   
#define EP1_INT                  0x02  // Endpoint 1, (Bulk-In) 
#define EP2_INT                  0x04  // Endpoint 2 
#define EP3_INT			 0x08  // Endpoint 3, (Bulk-Out)   
#define EP4_INT			 0x10  // Endpoint 4

//USB_INT_REG / USB_INT_EN_REG
#define SUSPEND_INT            	 0x01  
#define RESUME_INT               0x02  
#define RESET_INT                0x04  

//IN_CSR1
#define EPI_IN_PKT_READY         0x01  
#define EPI_UNDER_RUN		 0x04
#define EPI_FIFO_FLUSH		 0x08
#define EPI_SEND_STALL           0x10  
#define EPI_SENT_STALL           0x20  
#define EPI_CDT			 0x40	
#define EPI_WR_BITS              (EPI_FIFO_FLUSH|EPI_IN_PKT_READY|EPI_CDT) 
					//(EPI_FIFO_FLUSH) is preferred  (???)
//IN_CSR2
#define EPI_IN_DMA_INT_MASK	(1<<4)
#define EPI_MODE_IN		(1<<5)
#define EPI_MODE_OUT		(0<<5)
#define EPI_ISO			(1<<6)
#define EPI_BULK		(0<<6)
#define EPI_AUTO_SET		(1<<7)

//OUT_CSR1
#define EPO_OUT_PKT_READY        0x01  
#define EPO_OVER_RUN		 0x04  
#define EPO_DATA_ERROR		 0x08  
#define EPO_FIFO_FLUSH		 0x10
#define EPO_SEND_STALL           0x20  
#define EPO_SENT_STALL           0x40
#define EPO_CDT			 0x80	
#define EPO_WR_BITS              (EPO_FIFO_FLUSH|EPO_SEND_STALL|EPO_CDT)
					//(EPO_FIFO_FLUSH) is preferred (???)

//OUT_CSR2
#define EPO_OUT_DMA_INT_MASK	(1<<5)
#define EPO_ISO		 	(1<<6)
#define EPO_BULK	 	(0<<6)
#define EPO_AUTO_CLR		(1<<7)

//USB DMA control register
#define UDMA_IN_RUN_OB		(1<<7)
#define UDMA_IGNORE_TTC		(1<<7)
#define UDMA_DEMAND_MODE	(1<<3)
#define UDMA_OUT_RUN_OB		(1<<2)
#define UDMA_OUT_DMA_RUN	(1<<2)
#define UDMA_IN_DMA_RUN		(1<<1)
#define UDMA_DMA_MODE_EN	(1<<0)

#define rEP1_DMA_TTC	(rEP1_DMA_TTC_L+(rEP1_DMA_TTC_M<<8)+(rEP1_DMA_TTC_H<<16))
#define rEP2_DMA_TTC	(rEP2_DMA_TTC_L+(rEP2_DMA_TTC_M<<8)+(rEP2_DMA_TTC_H<<16))
#define rEP3_DMA_TTC	(rEP3_DMA_TTC_L+(rEP3_DMA_TTC_M<<8)+(rEP3_DMA_TTC_H<<16))
#define rEP4_DMA_TTC	(rEP4_DMA_TTC_L+(rEP4_DMA_TTC_M<<8)+(rEP4_DMA_TTC_H<<16))

#define ADDR_EP0_FIFO 		(0x520001c0) //Endpoint 0 FIFO
#define ADDR_EP1_FIFO		(0x520001c4) //Endpoint 1 FIFO
#define ADDR_EP2_FIFO		(0x520001c8) //Endpoint 2 FIFO
#define ADDR_EP3_FIFO		(0x520001cc) //Endpoint 3 FIFO
#define ADDR_EP4_FIFO		(0x520001d0) //Endpoint 4 FIFO

//If you chane the packet size, the source code should be changed!!!
#define EP0_PKT_SIZE             8	
#define EP1_PKT_SIZE             BULK_PKT_SIZE
#define EP3_PKT_SIZE             BULK_PKT_SIZE
#endif //_SC2440PDD_H_


